Binary-Domain Visual Processing: A High-Throughput and Fault-Tolerant Foundation for FPGA-Based On-Board Inference

Abstract

With the increasing deployment of high-resolution sensors in CubeSat missions, the demand for real-time, on-board data processing has outpaced the downlink bandwidth and power constraints of small-scale satellites. Traditional Deep Learning models based on floating-point arithmetic (Float32) are often unsuitable for CubeSat integration due to memory footprint, high-power consumption, and vulnerability to radiation-induced Single Event Upsets (SEUs)/Multiple Bit Upsets (MBU) in external memory. This paper proposes a binary-domain visual processing framework—Binary Graph Networks (BGN)—specifically designed for FPGA-based architectures like the Xilinx Zynq-7020 SoC. By leveraging a binary-weight and connection paradigm, the proposed architecture replaces costly multipliers with XNOR-Popcount logic, enabling high-throughput inference without relying on external DDR memory. We demonstrate that BGN models can be stored entirely within on-chip resources, reducing memory footprint by a minimum of 80%, while maintaining an accuracy degradation of only 3% to 4% compared to the Float32 models. Experimental results based on stochastic bit-flip injection indicate that under high error rates environments, the BGN framework maintains graceful degradation where traditional models suffer catastrophic failure.