Dynamic In-System Reprogramming and Validation of Fault-Tolerant FPGA Logic in Nanosatellite Embedded Systems

Abstract

This work presents the design, implementation, and rigorous validation of a dynamic reconfiguration system for Field-Programmable Gate Arrays (FPGAs), aimed at significantly improving the reliability and fault tolerance of embedded systems in space. Developed for the NASCERR nanosatellite project using the SmartFusion2 System-on-Chip (SoC) architecture, this system addresses the critical challenge of in-orbit firmware updates in resource-constrained environments. The proposed solution focuses on executing In-System Programming (ISP) managed by the integrated Cortex-M3 processor. A custom driver for external SPI Flash memory was developed to securely store the bitstream, circumventing hardware limitations and providing an essential backup mechanism. The integrity of the process is maintained through Cyclic Redundancy Check (CRC) during UART transmission and verified via the ISP authentication and programming phases. The system successfully reprogrammed the FPGA fabric and activated a Hamming Code Error Correction Code (ECC) module. Crucially, a subsequent test confirmed 100% error correction of injected single-bit errors, providing empirical proof of the new design’s functional integrity. Comparative analysis confirms that the ISP via SPI approach offers a superior transfer rate and reliability compared to UART, a factor critical for mission success.